Professional Experience

2015-Present

Research Scientist

Intel Labs

Neuromorphic Systems Architect

2008-2015

Research Assistant

Cornell AVLSI Group (now Yale)

Asynchronous Circuit Designer

2012

Graduate Intern, Technical

Intel Corporation

Asynchronous Circuit Designer

2007

Intern

DEKA Research and Development

Systems Designer

Education

2016

Ph.D., Electrical & Computer Eng.

Cornell University

Thesis: A Simple Methodology for Design Tradeoff Analysis in Asynchronous Circuits

2014

M.S., Electrical & Computer Eng.

Cornell University

2008

B.S., Electrical & Computer Eng.

Franklin W. Olin College of Engineering

Honors, Awards, Fellowships, and Certifications

2019

Gordy Award

Intel Labs

Excellence in Collaboration

2018

Gordy Award

Intel Labs

Technical Innovation

2010

NSF Graduate Research Fellowship

National Science Foundation

Honorable Mention

2010

Intern Engineer

NCEES

Fundamentals of Engineering

2009

Amateur Extra Radio Operator

Federal Communications Commission

KC2WAC

2008-2009

Jacobs Fellowship

Cornell University

Full Fellowship

2004-2008

Olin Scholarship

Franklin W. Olin College of Engineering

Full Scholarship

Teaching Experience

2020

Adjunct Lecturer

Olin College

Taught ENGR3410: Computer Architecture for a class of 30 students with the support of six teaching assistants. Covered Digital Logic, Digital Arithmetic, Design Evaluation, Single Cycle CPUs, and the basics of Computer Organization and Architecture. ENGR3410 has an involved lab component in which students design, implement, and simulate various structures in Verilog, ranging from simple adders to a single-cycle MIPS CPU. The final deliverable for the course is a Verilog implementation of a complex finite state machine, either an extension of the single cycle CPU or some other equivalent proect.

2013-2015

Senior Grad Student

Cornell University

Along with two other senior grad students, informally assumed leadership and advisory role for the AVLSI research group at the Ithaca, NY Cornell University campus. This was in direct response to Professor Rajit Manohar joining the Cornell Tech faculty at the NYC Cornell Tech campus in 2013, leaving day-to-day operations of his research lab in Ithaca to the remaining senior graduate students. Advised junior PhD students on projects and papers, oversaw several Masters of Engineering students' capstone projects, and managed Bachelors of Science interns.

2014

Teaching Assistant

CURIE Academy

Led a team of TAs during a week-long summer academy on IoT and embedded devices for 60 high school girls. Set up IoT infrastructure for laboratory work and advised students during the course of their lab work and final projects.

2008

Teaching Assistant

Cornell University

Served as a TA for an introductory class on VLSI design, holding recitation sessions and office hours, grading papers, and overseeing and advising students on VLSI projects.

2008

Self-Study Advisor

Franklin W. Olin College of Engineering

Served as the official advisor for two undergraduate students undertaking a self-study course on power electronics for credit. Gave targeted lectures and guidance on the students' final project.

2006-2008

Teaching Assistant

Franklin W. Olin College of Engineering

Served as a TA (NINJA in the Olin parlance) for the first-year engineering courses Engineering of Compartment Systems and Engineering of Distributed Systems for three consecutive years, and as the head TA for the last two years. Served as the TA for the Signals and Systems and Intro to Analog and Digital Communication. All four courses involved leading recitation sessions, overseeing lab work, office hours, and of course grading.

Project Experience

2020

Intel Pohoiki Springs

Intel Labs

Architected and delivered Pohoiki Springs, a 5 RU 19" rackmount system containing 768 Intel Loihi chips, providing access to a total of 100 million spiking neurons with plastic synapses for the Intel Neuromorphic Research Community.

2018

Intel Nahuku

Intel Labs

Architected and installed Nahuku, a desktop-form factor, 32-chip Intel Loihi system into a Neuromorphic research cloud provided by Intel Labs to the Intel Neuromorphic Research Community. Each Nahuku system provides 4 million spiking neurons for neuromorphic algorithms research.

2018

Intel Kapoho Bay

Intel Labs

Architected and delivered Kapoho Bay, a USB-stick-form-factor Intel Loihi system, to neuromorphic researchers less than a year after Loihi silicon return. Kapoho Bay is widespread use amongst the Intel Neuromorphic Research Community for embedded use cases and algorithmic prototyping purposes such as gesture recognition.

2017

Intel Loihi

Intel Labs

Designed and implemented the Intel Loihi Neuromorphic Research Chip and preceding test chips as part of a small silicon team within Intel labs. Lead silicon power on effort as well as the design and delivery of initial system prototypes to neuromorphic researchers, both internal and external to Intel.

2008-2015

Asynchronous VLSI

Cornell University

Designed and implemented seven asynchronous, full-custom ASICs and test chips as a part of student led teams over seven years. ASICs ranged from early spiking neural net processors, to FPGAs, to asynchronous microprocessors.

Papers

2020

Neuromorphic Nearest-Neighbor Search Using Intel’s Pohoiki Springs
E. Paxon Frady, Garrick Orchard, David Florey, Nabil Imam, Ruokun Liu, Joyesh Mishra, Jonathan Tse, Andreas Wild, Friedrich T. Sommer, Mike Davies
NICE 2020
arXiv

2018

Loihi Asynchronous Neuromorphic Research Chip
Andrew Lines, Prasad Joshi, Ruokun Liu, Steve McCoy, Jonathan Tse, Yi-Hsin Weng, Mike Davies
2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
DOI

Loihi: A Neuromorphic Manycore Processor with On-Chip Learning
Mike Davies, Narayan Srinivasa, Tsung-Han Lin, Gautham Chinya, Yongqiang Cao, Sri Harsha Choday, Georgios Dimou, Prasad Joshi, Nabil Imam, Shweta Jain, Yuyun Liao, Chit-Kwan Lin, Andrew Lines, Ruokun Liu, Deepak Mathaikutty, Steve McCoy, Arnab Paul, Jonathan Tse, Guruguhanathan Venkataramanan, Yi-Hsin Weng, Andreas Wild, Yoonseok Yang, Hong Wang
IEEE Micro, Volujme 38, Issue: 1, January/February 2018.
DOI

2015

A Bibliometric Analysis of Privacy and Ethics in IEEE Security and Privacy
Jonathan Tse, Dawn E. Schrader, Dipayan Ghosh, Tony Liao, and David Lundie.
Ethics and Information Technology, Volume 17, Issue 2, June 2015.
DOI

AES Software-Hardware Co-Design in WSN
Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar.
Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems, May 2015.
DOI

Automatic Obfuscated Cell Layout for Trusted Split-Foundry Design
Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, and Rajit Manohar.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, May 2015.
DOI

2014

ULSNAP: An Ultra-low Power Event-Driven Microcontroller for Sensor Network Nodes
Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, and Rajit Manohar.
Proceedings of the International Symposium on Quality Electronic Design, March 2014.
DOI

2013

A Bit of Analysis on Self-Timed Single-Bit On-Chip Links.
Jonathan Tse, Benjamin Hill, and Rajit Manohar.
Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems, May 2013.
DOI | Slides

A Split-Foundry Asynchronous FPGA
Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar.
Proceedings of the IEEE Custom Integrated Circuits Conference, September 2013.
DOI

NanoMesh: An Asynchronous Kilo-Core System-on-Chip
Jonathan Tse and Andrew Lines.
Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems, May 2013.
DOI | Slides

Neural Spiking Dynamics in Asynchronous Digital Circuits
Nabil Imam, Kyle Wecker, Jonathan Tse, Robert Karmazin, and Rajit Manohar.
Proceedings of the IEEE 2013 International Joint Conference on Neural Networks, August 2013.
DOI

2010

Static Power Reduction Techniques for Asynchronous Circuits
Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar.
Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems, May 2010.
DOI | Slides

Professional Activities

Journal Reviewer

  • IEEE Transactions on Circuits and Systems II

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Patents

Neuromorphic Core and Chip Traffic Control
Michael I. Davies, Andrew M. Lines, Jonathan Tse
Patent Pending, Filed Dec 12, 2016

Systems and Methods for Zero-Delay Wakeup for Power Gated Asynchronous Pipelines.
Rajit Manohar, Carlos Otero, Jonathan Tse
Patent Granted, Dec 27, 2016