Abstract

Innovative asynchronous circuits are central to the Ethernet switch chips from Intel’s Switch and Router Division (formerly Fulcrum Microsystems). These circuits are complex, and it can be hard to gauge their benefits since there are few direct comparisons. For this paper, we apply the technology and tool flow developed for these commercial products to a familiar benchmark: a network of general purpose processors on a chip. The processor is a single-issue 32-bit integer RISC core, a from- scratch implementation mostly compatible with the MIPS R3000. The network uses a 16-port 32-bit fully connected Nexus crossbar. We achieve greater scalability by linking these crossbars in a 2D mesh with clusters of 8 cores and 4 cardinal and 4 diagonal links per tile. Each core has 64KB of local memory and can access the memory of any other core in the mesh. Our design makes heavy use of the Proteus synthesis, place & route flow, as well as existing custom cells. It required only a few man-months of effort to develop a complete gate-level design and physical floor- plan which can run simple C programs such as Dhrystone. A few more man-months will produce a test chip, expected in 2013.

Authors

Jonathan Tse and Andrew Lines

Publication

Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems, May 2013.