Abstract

We present a study of five different self-timed single- bit on-chip links implemented in 90nm, 65nm, and 45nm process technologies. These include representative examples of Quasi Delay-Insensitive, single-track, ternary, and voltage-scaled links, as well as a link of our own design intended to minimize wire usage. We characterize the tradeoffs between throughput, energy, and area for planar wiring as well as 3D through- silicon vias. We also describe our multi-objective optimization framework for exploring this parameter space.

Authors

Jonathan Tse, Benjamin Hill, and Rajit Manohar

Publication

Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems, May 2013.